Senior Digital Design Engineer /Principal Digital Design Engineer- PCIE Design 6 views

Senior Digital Design Engineer /Principal Digital Design Engineer- PCIE Design

Mulya Technologies Company Location Bengaluru, Karnataka, India

Senior Digital Design Engineer /Principal Digital Design Engineer- PCIE Design

Job description

Location: Bangalore

  • Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers, enterprise, and WLAN applications.
  • The transition to 10Gb Ethernet and Multi-Gig Ethernet is currently underway, driven by the consolidation of data in the cloud and the mobile revolution.
  • Its 10GBASE-T and PHY product lines lead the market with low-power, high-performance, and high-density silicon solutions

Location: Bangalore

SMTS/Principal ASIC Design Engineer РPCI Design and Integration (post Graduate is a plus)


  • 5-18 yrs years of ASIC RTL Design experience and Verilog/System Verilog proficiency
  • Experience with multiple clocks and power domains
  • Extensive experience in integration and validation of high-speed PCIe IP core (including the controller and PHY SerDes)
  • Experience with PCIe protocol analyzers and debug
  • Familiarity with PCIe driver and application software for Linux/Windows
  • RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking application
  • Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals
  • Review vendor IP integration guidelines and verify the compliance throughout the design flow
  • Participate in the design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality
  • Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals
  • Be able to work and communicate with multi-site teams
  • Responsible for the review of netlist releases (pre/post-route/eco, block/chip)
  • ASIC product lifecycle experience (requirements, design, implementation, test and post-silicon validation)


Seniority Level

Mid-Senior level


Employment Type


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